1. The Field of the Invention
The present invention relates to field emission devices. More particularly, the present invention relates to field emission devices having a buffer layer, and to methods of making and using the field emission devices.
2. The Relevant Technology
Integrated circuits are currently manufactured by an elaborate process in which semiconductor devices, insulating films, and patterned conducting films are sequentially constructed in a predetermined arrangement on a semiconductor substrate. In the context of this document, the term "semiconductor substrate" is defined to mean any construction comprising semiconductive material, including but not limited to bulk semiconductive material such as a semiconductive wafer, either alone or in assemblies comprising other materials thereon, and semiconductive material layers, either alone or in assemblies comprising other materials. The term "substrate" refers to any supporting structure. As used herein, "field emission device" is defined to mean any construction for emitting electrons in the presence of an electrical field, including but not limited to an electron emission tip or tip either alone or in assemblies comprising other materials or structures. "Electron emission apparatus" refers to one or more field emission devices or any structure or product including one or more field emission devices.
Recently, miniaturization of structures within integrated circuits has focused attention and effort to incorporating field emission devices within semiconductor substrates. A field emission device typically includes an electron emission tip, or tip, configured for emitting a flux of electrons upon application of an electric field to the field emission device. An array of miniaturized field emission devices can be arranged on a plate and used for forming a visual display on a display panel. Indeed, field emission devices have been shown to be a promising alternative to cathode ray tube display devices. For example, field emission devices may be used in making flat panel display devices for providing visual display for computers, telecommunication, and other graphics applications. Flat panel display devices typically have a greatly reduced thickness compared to the generally bulky cathode ray tubes.
Field emission devices ordinarily include various structures formed from successive layers during the manufacturing process. FIG. 1 illustrates a portion of a conventional flat panel display, including a plurality of field emission devices. Flat panel display 10 comprises a baseplate 12 and a faceplate 14. Baseplate 12 includes substrate 16, which is preferably formed from an insulative glass material. Column interconnects 18 are formed and patterned over substrate 16. The purpose and function of column interconnects 18 is disclosed in greater detail below. Furthermore, a resistor layer 20, which is also discussed in greater detail below, may be disposed over column interconnects 18. Electron emission tips 22 are formed over substrate 16 at the sites from which electrons are to be emitted, and may be constructed in an etching process from a layer of amorphous silicon that has been deposited over substrate 16. Electron emission tips 22 are protrusions that may have one of many shapes, such as pyramids, cones, or other geometries that terminate at a fine point for the emission of electrons.
An extraction grid 24, or gate, which is a conductive structure that supports a positive charge relative to the electron emission tips 22 during use, is separated from substrate 16 with a dielectric layer 26. Extraction grid 24 includes openings 28 through which electron emission tips 22 are exposed. Dielectric layer 26 electrically insulates extraction grid 24 from electron emission tips 22 and the associated column interconnects which electrically connect the emission tips with a voltage source 30.
Faceplate 14 includes a plurality of pixels 32, which comprise cathodoluminescent material that generates visible light upon being excited by electrons emitted from electron emission tips 22. For example, pixels 32 may be red/green/blue full-color triad pixels. Faceplate 14 further includes a substantially transparent anode 34 and a glass or another transparent panel 36. Spatial support structures 38 are disposed between baseplate 12 and faceplate 14 and prevents the faceplate from collapsing onto the baseplate due to air pressure differentials between the opposite sides of the faceplate. In particular, the gap between faceplate 14 and baseplate 12 is typically evacuated, while the opposite side of the faceplate generally experiences ambient atmospheric pressure.
The flat panel display is operated by generating a voltage differential between electron emission tips 22 and grid structure 24 using voltage source 30. In particular, a negative charge is applied to electron emission tips 22, while a positive charge is applied to grid structure 24. The voltage differential activates electron emission tips 22, whereby a flux of electrons 40 is emitted therefrom. In addition, a relatively large positive charge is applied to anode 34 using voltage source 30, with the result that flux of electrons 40 strikes the faceplate. The cathodoluminescent material of pixels 32 is excited by the impinging electrons, thereby generating visible light. The coordinated activation of multiple electron emission tips over the flat panel display 10 may be used to produce a visual image on faceplate 16.
FIGS. 2 and 3 further illustrate field emission devices of the prior art. In particular, electron emission tips 22 are grouped into discrete emitter sets 42, in which the bases of the electron emission tips in each set are commonly connected. As shown in FIG. 3, for example, emitter sets 42 are configured into columns (e.g., C.sub.1 -C.sub.3) in which the individual emitter sets 42 in each column are commonly connected. Additionally the extraction grid 24 is divided into grid structures, with each emitter set 42 being associated with an adjacent grid structure. In particular, a grid structure is a portion of extraction grid 24 that lies over a corresponding emitter set 42 and has openings 28 formed therethrough. The grid structures are arranged in rows (e.g., R.sub.1 -R.sub.3) in which the individual grid structures are commonly connected in each row. Such an arrangement allows an X-Y addressable array of grid-controlled emitter sets. The two terminals, comprising the electron emission tips 22 and the grid structures, of the three terminal cold cathode emitter structure (where the third terminal is anode 34 in faceplate 14 of FIG. 1) are commonly connected along such columns and rows, respectively, by means of high-speed interconnects. In particular, column interconnects 18 are formed over substrate 16, and row interconnects 44 are formed over the grid structures. In operation, a specific emitter set is selectively activated by producing a voltage differential between the specific emission set and the associated grid structure. The voltage differential may be selectively established through corresponding drive circuitry that generates row and column signals that intersect at the location of the specific emitter set. Referring to FIG. 3, for example, a row signal along for R.sub.2 of the extraction grid 24 and a column signal along column C.sub.1 of emitter sets 42 activates the emitter set at the intersection of row R.sub.2 and column C.sub.1. The voltage differential between the grid structure and the associated emitter set produces a localized electric field that causes emission of electrons from the selected emitter set.
Early field emission devices were assembled without resistor layer 20 and suffered from uneven emission between different electron emission tips 22, with the result that noticeably bright and dim spots were produced on the screens of the flat panel displays. The problem of uneven emission was significantly reduced by including resistor layer 20, shown in FIGS. 1 and 2, between column interconnects 18 and electron emission tips 22. Resistor layer 20 acts as ballast against excessive current through electron emission tips 22, thereby making electron emission roughly uniform among different electron emission tips. Moreover, in the absence of resistor layer 20, short circuiting between column interconnects 18 and row interconnects 44 was sometimes observed.
Significant problems with the resistor layer in the above described device are evident in the prior art. The resistor layer is likely to have at least occasional "pinhole" defects or other discontinuities, which may lead to breakdown of the resistor layer, which can in turn cause short circuiting and failure of the device. Pinhole defects are commonly created during, for example, plasma enhanced chemical vapor deposition (PECVD) of a silane (SiH.sub.4) and diborane (B.sub.2 H.sub.6) mixture to form a boron-doped amorphous silicon resistor layer. In the high pressures of favored high throughput PECVD processes, particles are formed by homogeneous nucleation, in which radicals in the mixture react. These particles may come to rest on the forming resistor layer, thereby causing pinhole defects. Discontinuities in the resistor layer can cause the loss of the benefits for which the resistor layer was used in the first place. Additionally, discontinuities in the resistor layer can present problems when subsequent etching or photolithographic processes are conducted, potentially causing delamination of various layers and other irregularities.
It has been found that the foregoing process of pinhole formation is especially prevalent when large display panels are manufactured. For example, display panels having sides measuring 10 inches or more are particularly prone to experiencing defects generated by homogeneous nucleation.
Reducing the pressure at which the boron-doped amorphous silicon resistor layer is formed will reduce the likelihood of pinhole and other related defects. However, reducing deposition pressure is unsatisfactory for other reasons. The deposition rate of silicon increases with increasing PECVD operating pressure. Accordingly, manufacturing time and expenses are reduced with high pressure. Additionally, high pressure PECVD produces amorphous silicon resistor layers that exhibit little sensitivity to light. In particular, the resistivity of an amorphous silicon layer formed in a PECVD process at a pressure in a range from about 1,200 milliTorr to about 1,500 milliTorr and at an operating power approaching about 300 W varies less than about 5% in response to the presence or absence of light generated during operation of a display panel. Lower pressure PECVD processes, such as those conducted at pressures in a range from about 500 milliTorr to about 800 milliTorr, generally cannot provide such light-insensitive amorphous silicon.
In view of the foregoing, it is clear that there exists a need for a field emission device that has a resistor layer, yet avoids the harmful consequences of pinhole defects. In particular, it would be desirable to provide a field emission device that can be produced using high throughput, high pressure PECVD, while avoiding breakdown conditions of the resistor layer, even if discontinuities in the resistor layer are present.